How many main phase of UVM? UVM thực chất là SystemVerilog template được thiết kế để chạy tuần tự các phase từ build_phase>>>connect_phase>>>end_of_elaboration_phase>>>start_of_simulation_phase>>>run_phase>>>extract_phase>>>check_phase>>>report_phase>>>extract_phase>>>final_phase 1>BUILD_PHASE: no runtime - tạo component (env/agent/driver/monitor/scoreboard), đọc & set config, factory override. 2>CONNECT_PHASE: no runtime - nối các kết nối TLM/analysis, nối sequencer–driver, monitor→scoreboard,
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