Advances in both the physical properties of chips and in design tools allow us build huge systems into “just a few” square millimeters. The problem is that modeling these systems at the ...

IP companies have heralded a new age in platform-based design for years – ever since semiconductor integration capacity reached the point where entire systems could theoretically be integrated into a ...

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As ...

With design complexity always on the rise and an increasing amount of embedded software encapsulation in designs today, engineering teams need to be concerned with power consumption in the initial ...

After many years of expectation, we're finally seeing increased use of generally usable methods of hardware design at an abstraction level higher than RTL. This is more than just behavioral level, as ...

SANTA CLARA, Calif. -- May 20, 2008-- EVE, the leader in hardware/software co-verification, will showcase an expanded library of standard transactors and a new custom transactor development tool ...

SLD: How long has NXP designed at the system-level for production chips? Frans Theeuwen: It depends on what you call ‘system-level design.’ We have been doing hardware/software co-verification ...