Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Design-Reuse

'Smart' verification moves beyond SystemVerilog 3.0

Functional verification is consuming an inordinate amount of the design cycle. Estimates vary, but most analysts and engineers agree that as much as 70 percent of the design cycle is consumed by ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
EDN

Zocalo zips assertions with Zazz

Zocalo Tech is shipping Zazza software tool with a graphical user interface that provides productivity gains and ease of use over manual instantiation of assertion checkers in IC designs.