EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Models for high-voltage transistors in a standard CMOS process

Designers of electronics and communications systems are constantly faced with the challenge of integrating greater functionality on less silicon area. Many of the system blocks – such as power ...
Nature

Analog Circuit Design Using MOS Transistors

Analog circuit design using MOS transistors represents a dynamic and rapidly evolving field that is integral to modern electronics. Exploiting the inherent advantages of MOS technology—such as ...
Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
Electronics Weekly

Updated: X-FAB adds to low-noise transistor portfolio

X-FAB has added three new low-noise transistors to its 180nm process node: a 1.8 V low-noise NMOS, a 3.3 V low-noise NMOS and a 3.3 V low-noise PMOS – all of which offer drastically reduced flicker ...
Design-Reuse

Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes

Advanced process technologies, such as 90nm, 65nm, 45nm and below, present significant power management challenges for high performance semiconductors. Chip designers face increasing challenges in ...