This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...

Editor’s Note: Demand for increasing functionality and performance in systems designs continues to drive the need for more memory even as hardware engineers balance the dynamics of system capability, ...

Data prefetching has emerged as a critical approach to mitigate the performance bottlenecks imposed by memory access latencies in modern computer architectures. By predicting the data likely to be ...