EDN

Synopsys’ New DesignWare DDR Explorer Tool Delivers Up to 20 Percent Improvement in DDR Memory Subsystem Efficiency

DesignWare DDR Explorer enables designers to optimize memory subsystems for power, performance and cost through a graphical simulation and analysis environment Explore and adjust Synopsys' DesignWare ...
Electronic Design

Digital Controller for DDR Memory

Powervation Ltd. announces sampling of PV3201, a new dual phase digital DC/DC controller with SVID interface. PV3201 complies with the Serial VID (SVID) communications protocol of Intel's VR12/VR12.5 ...
Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Design-Reuse

Global Unichip Selects Denali for DDR Memory System Deployment

Databahn DDR Controller IP and PHY Solutions Speeds Production of DDR1, DDR2 and Mobile DDR Memory Systems PALO ALTO, Calif. -- Feb. 20, 2007-- Denali Software, Inc., a world-leading provider of ...
Design-Reuse

Denali DDR Controller IP Product Enables Mobileye's Next-Generation Automotive Technology

PALO ALTO, Calif. -- Oct. 16, 2006-- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM ...
Semiconductor Engineering

DDR White Paper

DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, ...
Electronic Design

SVID-Enhanced Controller Maximizes DDR Memory Flexibility

The PV3201 dual-phase digital dc-dc controller developed by Powervation comes with a Serial VID (SVID) interface. Cork, Ireland: The PV3201 dual-phase digital dc-dc controller developed by Powervation ...
EDN

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...
Semiconductor Engineering

Time For A DDR Background Check

In this month’s blog we continue our discussion of power management, specifically looking at how architects can improve the energy efficiency of their SoC as it uses system memory. In March we teamed ...
Business Wire

Silicon Valley Startup Granted US Patent on Critical DDR2/DDR3 Timing Innovation for Chip Designs

SANTA CLARA, Calif.--(BUSINESS WIRE)--Uniquify, a Silicon Valley semiconductor IP start-up (http://www.uniquify.com), today announced that it has been granted a ...
Cloud Computing

Montage Technology launches Memory eXpander Controller

Integrated circuit company Montage Technology has launched its CXL 3.1 Memory eXpander Controller (MXC), which is currently being tested by some of its key customers, including AMD and Intel. The ...